There are two major types of random-access memory cells, dynamic and static. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods. Static random-access memories are so named because they do not require periodic refreshing.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.
FIG. 1A illustrates two conventional DRAM cells 10; each cell 10 includes a capacitor 14 and an access transistor 12. For each cell 10, the capacitor 14 has two connections located on opposite sides of the capacitor 14. The first connection is to a reference voltage Vr, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1”) of the memory circuit. The second capacitor connection is to the drain of the transistor 12. The gate of the transistor 12 is connected to a word line 18, and the source of the transistor is connected to a bit line 16. This connection enables the word line 18 to control access to the capacitor 14 by allowing or preventing a signal (a logic “0” or a logic “1”) on the bit line 16 to be written to or read from the capacitor 14. FIG. 1C shows a cross-sectional view of the DRAM cell 10. FIG. 1B shows a portion of a DRAM memory array comprising DRAM cells 10. In FIG. 1B, each cell 10 sharing a given bit line 16 does not share a common wordline 18, and each cell 10 sharing a common wordline 18 does not share a common bit line 16.
DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip. Cell sizes of six square feature area (6F2) to four square feature area (4F2) are desired (where F represents the minimum realizable photolithographic process dimension feature size). Isolation of devices on a DRAM memory thus becomes increasingly important as the size of each cell is decreased, thereby placing active areas (e.g., area 13 on FIG. 1B) of each cell in closer proximity to the active areas of other devices. Isolation is required in other integrated circuit structures as well.
Shallow trench isolation (STI) is one technique that can be used to isolate the active areas on a DRAM array or other integrated structures from one another. As shown in FIG. 1C, an isolation trench 17 formed in a substrate surface 1 may be used to isolate two adjacent DRAM memory cells, each having a capacitor 14, a transistor 12, and associated source/drain regions 19. In a typical STI isolation structure, a trench 17 is etched into the substrate and filled with one or more layers of dielectric material 15 to provide a physical and electrical barrier between adjacent active areas. Thus, an STI structure is formed by etching a trench and then filling it with a dielectric such as a chemical vapor deposited (CVD) or high density plasma (HDP) silicon oxide or silicon dioxide (SiO2). The filled trench is then planarized by a chemical mechanical planarization (CMP) or etch-back process so that the dielectric remains only in the trench and its top surface remains level with that of the silicon substrate.
To enhance the isolation further, ions may be implanted into the silicon substrate in the area directly beneath the trench (not shown). However, there is a drawback associated with ion implantation beneath the trench; as noted, for example, in S. Nag et al., “Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 micron Technologies,” IEEE IEDM, pp. 841-844 (1996), ion implantation beneath the trench can result in high current leakage. In particular, when ions are implanted in the substrate close to the edges of the trench, current leakage can occur at the junction between the active device regions and the trench.
Further, and referring to FIG. 1C, although deeper STI regions may provide better isolation, there is a limit to how deep the STI region can be made. If the STI region is too deep, filling the trench 17 with oxide layers 15 will result in voids 11 or cracks in the trench. Thus, there is a desire and need to isolate active areas of memory devices without relying on a deep or doped trench region.
Isolation gates have also been proposed for providing device isolation in high-density integrated circuits. These gates typically use a thick oxide layer, like silicon dioxide, but they still rely on conventional implants to provide a strong accumulation layer at the substrate surface. Thus, conventional isolation gates still facilitate the presence of gate-induced drain leakage (GIDL).
There is needed, therefore, an isolation structure which can be used in high density applications, such as DRAM memory devices. There also exists a need for a simple method of fabricating such an isolation structure.